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Coreboot

Coreboot is a free and open-source firmware replacement for proprietary BIOS/UEFI. It provides fast boot times, enhanced security through verified boot, and complete transparency of the firmware stack. Multiple porting efforts target Framework laptops, covering both AMD and Intel models123.

Background​

The Framework community has long requested coreboot support since the laptop's launch in 202114. In January 2022, Framework open-sourced their EC firmware, and the coreboot discussion became the main tracking thread for firmware liberation efforts1. Framework has stated that moving to open UEFI/BIOS solutions is "on the list of things that we are exploring"1.

AMD Ports​

Azalea (Framework 13 AMD Ryzen 7040 Series)​

Martin Roth (AMD firmware engineer) led experimental coreboot support for the Framework 13 AMD "Azalea" board (Ryzen 5 7640U / Ryzen 7 7840U). Announced in May 2024, this initial port uses AMD's FSP binary implementation (not openSIL) and is a proof-of-concept — suspend is not supported, boot times are longer due to full memory re-initialization, and flashing requires an SPI programmer567.

SpecificationDetails
CodenameAzalea
SoCAMD Ryzen 7040 "Phoenix" (Zen 4)
InitializationAMD FSP (binary)
Flash32 MiB, 1.8V WSON8, socketed on early boards
StatusExperimental, proof-of-concept
Documentationcoreboot docs

An important limitation is that AMD's FSP and openSIL for Phoenix are "not fully featured" — the port is explicitly not production quality and is not recommended for daily-driver use7.

Framework 16 "Lotus" + openSIL Port (2026)​

In March 2026, 9elements (Alicja Michalska) began porting coreboot with AMD openSIL (Open-Source Silicon Initialization) to the first-generation Ryzen 7000 series Framework 16, codenamed "Lotus"8910. This is a significant step as openSIL is AMD's open-source replacement for the proprietary AGESA binary blob, designed to be integrated directly into coreboot8910.

AMD released the Phoenix openSIL code in October 2025, enabling this work11. After approximately three months of effort, Alicja reported on July 17, 2026 that the port is "mostly working" — the Framework 16 boots Linux 7.1.4 with PSP DRAM training, both M.2 slots, both RAM slots, internal and external USB, integrated GPU (via Linux KMS), eDP display, AOAC peripherals, and EC functionality (power, AC/DC, fan control) all operational1112. Power draw is only ~200 mW higher than stock firmware and is expected to be tuned down further11.

Known remaining issues as of July 2026 include: EDK2 GOP init (GPU works only after Linux's KMS takes over), USB4/Thunderbolt causing RCU stalls, USB PHY tuning being slightly off on longer cables, and suspend (platform enters s0ix but the EC doesn't receive the notification — suspected ACPI bug)1112. Non-eDP video outputs (USB-C DP Alt Mode) also time out12.

Alicja plans to begin daily-driving the system with coreboot "relatively soon" and to start cleaning up and upstreaming the code in August 2026, with a live demo scheduled for COSCUP11. A Framework 13 (AMD Phoenix) openSIL port is expected to follow the Framework 16 work89. openSIL is AMD's roadmap for Zen 6 platforms — making these ports critical validation for the library's production readiness913.

Intel Ports​

Marigold (Framework 13 Intel Core Ultra Series 1 / Meteor Lake)​

Merged into coreboot in June 2026, Marigold supports the Framework 13 with Intel Core Ultra Series 1 (Meteor Lake). Most functionality works: eDP display, WiFi/Bluetooth, USB devices, camera, fingerprint reader, I2C HID touchpad and ALS sensor, keyboard media keys, audio, and HDMI audio over USB-C DP-Alt mode. Thunderbolt 4 / USB4 and S0ix support are implemented but not yet fully tested141516.

Coreboot commit 4ad42c2 adds the board with FSP binaries. Production systems ship with BootGuard fused, so coreboot images will not boot on fused units — development is done on unfused systems with socketed ROMs15.

Sakura (Framework 13 Pro Intel Core Ultra Series 3 / Panther Lake)​

Added in Framework's downstream coreboot repository, Sakura targets the Framework 13 Pro with Panther Lake (Core Ultra Series 3). Like Marigold, both ports are explicitly described in coreboot's documentation as "not officially supported by Framework" — they are proof-of-concept evaluations for internal feasibility, and BootGuard on production units prevents the images from booting on customer hardware1617.

Firmware Details​

ModelCodenameSoCInitStatus
Framework 13 AMD (7040)AzaleaRyzen 7040U (Phoenix)FSPExperimental5
Framework 16 AMD (7040)LotusRyzen 7040HS (Phoenix)openSILMostly working (Jul 2026)1112
Framework 13 Intel (Meteor Lake)MarigoldCore Ultra 1 (Meteor Lake)FSPUpstream1417
Framework 13 Pro Intel (Panther Lake)SakuraCore Ultra 3 (Panther Lake)FSPUpstream1617

Flashing​

All Framework coreboot ports require external hardware flashing (WSON8 test clip + 1.8V SPI programmer). Internal flashing is possible from a running coreboot image, but initial installation and recovery from a failed flash require hardware access. Backup of the original ROM is mandatory before attempting6715.

Limitations​

  • Suspend (S3/S0i3) is not supported on AMD ports57
  • Boot times are longer on AMD due to full memory retraining each boot (no APOB data save)5
  • USB4 has not been fully tested on Intel ports15
  • BootGuard on production Intel units prevents coreboot from booting unless unfused15
  • Binary blobs (FSP, AMD firmware) are still required — only openSIL provides a fully open initialization path58

Community & Industry Impact​

The porting efforts involve multiple firms and individuals:

  • Martin Roth (AMD) — Azalea proof-of-concept5
  • 9elements (Alicja Michalska) — openSIL port to Framework 16/138
  • 3mdeb — Parallel openSIL work on AMD EPYC and AM5 platforms8
  • Framework Computer — Downstream coreboot repo for Marigold/Sakura16

Successful coreboot ports would give Framework laptop owners complete firmware transparency, potential for custom boot logos, better long-term support independent of manufacturer updates, and reduced dependency on proprietary firmware blobs9. The collaboration between Framework, AMD (openSIL), and the coreboot community sets a benchmark for open firmware on modern laptops13.

Footnotes​

  1. [RESPONDED] Coreboot on the Framework Laptop — Framework Community (2021–2026) ↩ ↩2 ↩3 ↩4

  2. Coreboot — Official Website ↩

  3. Coreboot 24.05 Release — coreboot blog (May 2024) ↩

  4. Support #387: Support Framework Laptop — coreboot Issue Tracker ↩

  5. Framework 13 AMD Laptop Seeing Experimental Coreboot Port — Phoronix (May 2024) ↩ ↩2 ↩3 ↩4 ↩5 ↩6

  6. Framework 13 AMD Coreboot Port — Forum Post #418 — Framework Community (Martin Roth) ↩ ↩2

  7. coreboot Gerrit: Azalea Board Documentation — coreboot (Martin Roth) ↩ ↩2 ↩3 ↩4

  8. Framework 16 Gen1 Seeing Coreboot + AMD openSIL Port — Phoronix (March 2026) ↩ ↩2 ↩3 ↩4 ↩5 ↩6

  9. Coreboot/OpenSIL Porting Underway for AMD FW16 — Framework Community ↩ ↩2 ↩3 ↩4 ↩5

  10. 9elements — Coreboot + openSIL on Framework 16 — LavX News (March 2026) ↩ ↩2

  11. Framework 16 AMD Ryzen 7040 Series — Phoenix OpenSIL status update — Alicja Michalska, 9elements (July 2026) ↩ ↩2 ↩3 ↩4 ↩5 ↩6

  12. mb/framework: Add Laptop 16 (Lotus) — Gerrit Change 89634 — coreboot Gerrit (Alicja Michalska) ↩ ↩2 ↩3 ↩4

  13. AMD openSIL Project — AMD ↩ ↩2

  14. Framework Computer Making Progress On Coreboot For Intel Laptops — Phoronix (June 2026) ↩ ↩2

  15. coreboot commit: mb/framework: Add marigold — coreboot GitHub ↩ ↩2 ↩3 ↩4 ↩5

  16. Framework Laptop 13 Intel Core Ultra Series 1 (Marigold) — coreboot docs — coreboot ↩ ↩2 ↩3 ↩4

  17. coreboot 26.06 Release — coreboot blog (June 2026) ↩ ↩2 ↩3